The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. For example, the invention can be preferably used for a semiconductor device including a metal-insulation-semiconductor field-effect transistor (MISFET) that operates at a high voltage of several tens of volts.
The semiconductor device is configured such that a number of circuit elements such as a metal-oxide semiconductor field-effect transistor (MOSFET), a resistance, and a capacitor are provided on a main surface of a semiconductor substrate composed of single-crystal silicon or the like, and the circuit elements are coupled to one another so as to perform required circuit operations and/or functions.
Japanese Unexamined Patent Application Publication No. Hei 08(1996)-130308 discloses a technique for improving a semiconductor device including a plurality of MOSFETs isolated from one another by channel stopper regions, the technique allowing the withstand voltage of each MOSFET to be increased and suppressing current leakage between a source region and a drain region of the MOSFET.
In the MOSFET described in JP-A-1996-130308, at least one of the source and drain regions is configured of a low-concentration region and a high-concentration region, each region having a conduction type opposite to that of a semiconductor substrate, and a channel stopper region having the same conduction type as that of the semiconductor substrate is provided below an element-isolating field oxide film. An offset region is provided to separate between the channel stopper region and each of the source region and the drain region. An end of the channel stopper region projects from a position below the field oxide film toward a region (a channel region) directly below a gate electrode so as to be in contact with the low-concentration region.
According to the MOSFET described in Japanese Unexamined Patent Application Publication No. Hei 08(1996)-130308, the offset region is provided between the channel stopper region and each of the source and drain regions, thereby even if the channel stopper region is increased in impurity concentration, reverse characteristics of a pn junction are not degraded, so that occurrence of a leakage current is suppressed. In addition, since the channel stopper region is in contact with the low-concentration region directly below the gate electrode, no inversion phenomenon occurs in a semiconductor layer (well region) adjacent to the channel region, and current leakage is prevented.